In TCL Script/python script, add few lines of data where the specific line occurs

Question

Here I have 2 files 1st file is XXXX.lib and 2nd file is temp.txt,
In 2nd file is I want to fetch each 10 lines and add this to 1st file where the specific format is found if {[string match "pin*]*" $line]} { It will give multiple matches but i want to add those lines where the 0th pin will start.

the code what i tried is.

set file_temp [open "temp.txt" r]
set temp_contents [read $file_temp]
close $file_temp

set file_2nd [open "rx_clkgen_tdl_ss_0.675v_m40c1.lib" r]
set file_2nd_contents [read $file_2nd]
close $file_2nd

set lines [split $temp_contents "n"]

foreach line $lines {
    if {[string first "bus(" $line] != -1} {
        # Extract the bus name and bus type
        set bus_name [string range $line 5 [string first ")" $line]]
        set bus_type [string range $line [string last "bus_type : " $line]+12 end]

        # Check if the bus name already exists in the 2nd file
        if {[string first "pin*$bus_name*" $file_2nd_contents] == -1} {

            # If not, append the line to the 2nd file
            set file_2nd [open "rx_clkgen_tdl_ss_0.675v_m40c1.lib" a]
            puts $file_2nd "pin*$bus_name*"
            puts $file_2nd " type : $bus_type"
            puts $file_2nd ""
            close $file_2nd
        }
    }
}

the temp file consists of this data.

type (bus0) {
 base_type : array ;
 data_type : bit ;
 bit_width : 7 ;
 bit_from : 0 ;
 bit_to : 6 ;
 downto : true ;
}
bus (DCC_SEL) {
 bus_type : bus0


type (bus1) {
 base_type : array ;
 data_type : bit ;
 bit_width : 9 ;
 bit_from : 0 ;
 bit_to : 8 ;
 downto : true ;
}
bus (NDE_DLY_SEL) {
 bus_type : bus1


type (bus2) {
 base_type : array ;
 data_type : bit ;
 bit_width : 4 ;
 bit_from : 0 ;
 bit_to : 3 ;
 downto : true ;
}
bus (PCLK_PH_SEL) {
 bus_type : bus2


type (bus3) {
 base_type : array ;
 data_type : bit ;
 bit_width : 10 ;
 bit_from : 0 ;
 bit_to : 9 ;
 downto : true ;
}
bus (PI_SEL) {
 bus_type : bus3


type (bus4) {
 base_type : array ;
 data_type : bit ;
 bit_width : 6 ;
 bit_from : 0 ;
 bit_to : 5 ;
 downto : true ;
}
bus (SCLK_DLY_SEL) {
 bus_type : bus4


type (bus5) {
 base_type : array ;
 data_type : bit ;
 bit_width : 4 ;
 bit_from : 0 ;
 bit_to : 3 ;
 downto : true ;
}
bus (SPARE) {
 bus_type : bus5

where the XXXX.lib file cosist this data.

  cell (rx_clkgen_tdl) {
    area : 2025;
    cell_leakage_power : 0;
    dont_use : true;
    interface_timing : true;
    pg_pin (VDD) {
      direction : inout;
      pg_type : primary_power;
      voltage_name : "VDD";
    }
    pg_pin (VSS) {
      direction : inout;
      pg_type : primary_ground;
      voltage_name : "VSS";
    }
    pin ("BITS_CLK2QDLY[0]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.00132887;
      rise_capacitance : 0.00132887;
      fall_capacitance : 0.00132646;
    }
    pin ("BITS_CLK2QDLY[1]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.00132887;
      rise_capacitance : 0.00132887;
      fall_capacitance : 0.00132646;
    }
    pin ("BITS_DCC_MAIN[0]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000557936;
      rise_capacitance : 0.000557936;
      fall_capacitance : 0.000557719;
    }
    pin ("BITS_DCC_MAIN[1]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000557936;
      rise_capacitance : 0.000557936;
      fall_capacitance : 0.000557719;
    }
    pin ("BITS_DCC_MAIN[2]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000557936;
      rise_capacitance : 0.000557936;
      fall_capacitance : 0.000557719;
    }
    pin ("BITS_DCC_MAIN[3]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000557936;
      rise_capacitance : 0.000557936;
      fall_capacitance : 0.000557719;
    }
    pin ("BITS_DCC_MAIN[4]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000557936;
      rise_capacitance : 0.000557936;
      fall_capacitance : 0.000557719;
    }
    pin ("BITS_DCC_MAIN[5]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000557936;
      rise_capacitance : 0.000557936;
      fall_capacitance : 0.000557719;
    }
    pin ("BITS_DCC_MAIN[6]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.00193895;
      rise_capacitance : 0.00193895;
      fall_capacitance : 0.0019222;
    }
    pin ("BITS_FIXDLY_MAIN[0]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399907;
      rise_capacitance : 0.000399907;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_FIXDLY_MAIN[1]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399907;
      rise_capacitance : 0.000399907;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_FIXDLY_MAIN[2]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399907;
      rise_capacitance : 0.000399907;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_FIXDLY_MAIN[3]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399907;
      rise_capacitance : 0.000399907;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_FIXDLY_MAIN[4]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399913;
      rise_capacitance : 0.000399913;
      fall_capacitance : 0.00039965;
    }
    pin ("BITS_FIXDLY_MAIN[5]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399913;
      rise_capacitance : 0.000399913;
      fall_capacitance : 0.000399653;
    }
    pin ("BITS_FIXDLY_MAIN[6]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399913;
      rise_capacitance : 0.000399913;
      fall_capacitance : 0.000399653;
    }
    pin ("BITS_FIXDLY_MAIN[7]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399904;
      rise_capacitance : 0.000399904;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_NDE_DLY[0]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399904;
      rise_capacitance : 0.000399904;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_NDE_DLY[1]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399904;
      rise_capacitance : 0.000399904;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_NDE_DLY[2]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399904;
      rise_capacitance : 0.000399904;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_NDE_DLY[3]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399904;
      rise_capacitance : 0.000399904;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_NDE_DLY[4]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399904;
      rise_capacitance : 0.000399904;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_NDE_DLY[5]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399904;
      rise_capacitance : 0.000399904;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_NDE_DLY[6]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399904;
      rise_capacitance : 0.000399904;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_NDE_DLY[7]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399904;
      rise_capacitance : 0.000399904;
      fall_capacitance : 0.000399639;
    }
    pin (BIT_HIRANGE) {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000799716;
      rise_capacitance : 0.000799716;
      fall_capacitance : 0.000799202;
    }

the expected result/update in XXXX.lib is.

  cell (rx_clkgen_tdl) {
    area : 2025;
    cell_leakage_power : 0;
    dont_use : true;
    interface_timing : true;
    pg_pin (VDD) {
      direction : inout;
      pg_type : primary_power;
      voltage_name : "VDD";
    }
    pg_pin (VSS) {
      direction : inout;
      pg_type : primary_ground;
      voltage_name : "VSS";
    }
type (bus0) {
      base_type : array ;
      data_type : bit ;
      bit_width :  2;
      bit_from :  1;
      bit_to :  0;
      downto : true ;
    }

bus (BITS_CLK2QDLY) {
  bus_type : bus0
    pin ("BITS_CLK2QDLY[0]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.00132887;
      rise_capacitance : 0.00132887;
      fall_capacitance : 0.00132646;
    }
    pin ("BITS_CLK2QDLY[1]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.00132887;
      rise_capacitance : 0.00132887;
      fall_capacitance : 0.00132646;
    }
 }

type (bus1) {
      base_type : array ;
      data_type : bit ;
      bit_width :  7;
      bit_from :  6;
      bit_to :  0;
      downto : true ;
    }

bus (BITS_DCC_MAIN) {
  bus_type : bus1
    pin ("BITS_DCC_MAIN[0]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000557936;
      rise_capacitance : 0.000557936;
      fall_capacitance : 0.000557719;
    }
    pin ("BITS_DCC_MAIN[1]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000557936;
      rise_capacitance : 0.000557936;
      fall_capacitance : 0.000557719;
    }
    pin ("BITS_DCC_MAIN[2]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000557936;
      rise_capacitance : 0.000557936;
      fall_capacitance : 0.000557719;
    }
    pin ("BITS_DCC_MAIN[3]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000557936;
      rise_capacitance : 0.000557936;
      fall_capacitance : 0.000557719;
    }
    pin ("BITS_DCC_MAIN[4]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000557936;
      rise_capacitance : 0.000557936;
      fall_capacitance : 0.000557719;
    }
    pin ("BITS_DCC_MAIN[5]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000557936;
      rise_capacitance : 0.000557936;
      fall_capacitance : 0.000557719;
    }
    pin ("BITS_DCC_MAIN[6]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.00193895;
      rise_capacitance : 0.00193895;
      fall_capacitance : 0.0019222;
    }
 }

type (bus2) {
      base_type : array ;
      data_type : bit ;
      bit_width :  8;
      bit_from :  7;
      bit_to :  0;
      downto : true ;
    }

bus (BITS_FIXDLY_MAIN) {
  bus_type : bus2
    pin ("BITS_FIXDLY_MAIN[0]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399907;
      rise_capacitance : 0.000399907;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_FIXDLY_MAIN[1]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399907;
      rise_capacitance : 0.000399907;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_FIXDLY_MAIN[2]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399907;
      rise_capacitance : 0.000399907;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_FIXDLY_MAIN[3]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399907;
      rise_capacitance : 0.000399907;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_FIXDLY_MAIN[4]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399913;
      rise_capacitance : 0.000399913;
      fall_capacitance : 0.00039965;
    }
    pin ("BITS_FIXDLY_MAIN[5]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399913;
      rise_capacitance : 0.000399913;
      fall_capacitance : 0.000399653;
    }
    pin ("BITS_FIXDLY_MAIN[6]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399913;
      rise_capacitance : 0.000399913;
      fall_capacitance : 0.000399653;
    }
    pin ("BITS_FIXDLY_MAIN[7]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399904;
      rise_capacitance : 0.000399904;
      fall_capacitance : 0.000399639;
    }
 }

type (bus3) {
      base_type : array ;
      data_type : bit ;
      bit_width :  8;
      bit_from :  7;
      bit_to :  0;
      downto : true ;
    }

bus (BITS_NDE_DLY) {
  bus_type : bus3
    pin ("BITS_NDE_DLY[0]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399904;
      rise_capacitance : 0.000399904;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_NDE_DLY[1]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399904;
      rise_capacitance : 0.000399904;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_NDE_DLY[2]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399904;
      rise_capacitance : 0.000399904;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_NDE_DLY[3]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399904;
      rise_capacitance : 0.000399904;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_NDE_DLY[4]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399904;
      rise_capacitance : 0.000399904;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_NDE_DLY[5]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399904;
      rise_capacitance : 0.000399904;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_NDE_DLY[6]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399904;
      rise_capacitance : 0.000399904;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_NDE_DLY[7]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399904;
      rise_capacitance : 0.000399904;
      fall_capacitance : 0.000399639;
    }
}
    pin (BIT_HIRANGE) {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000799716;
      rise_capacitance : 0.000799716;
      fall_capacitance : 0.000799202;
    }

but what i am getting this is:

type (bus0) {
 base_type : array ;
 data_type : bit ;
 bit_width : 7 ;
 bit_from : 0 ;
 bit_to : 6 ;
 downto : true ;
}
bus (DCC_SEL) {
 bus_type : bus0


type (bus1) {
 base_type : array ;
 data_type : bit ;
 bit_width : 9 ;
 bit_from : 0 ;
 bit_to : 8 ;
 downto : true ;
}
bus (NDE_DLY_SEL) {
 bus_type : bus1


type (bus2) {
 base_type : array ;
 data_type : bit ;
 bit_width : 4 ;
 bit_from : 0 ;
 bit_to : 3 ;
 downto : true ;
}
bus (PCLK_PH_SEL) {
 bus_type : bus2


type (bus3) {
 base_type : array ;
 data_type : bit ;
 bit_width : 10 ;
 bit_from : 0 ;
 bit_to : 9 ;
 downto : true ;
}
bus (PI_SEL) {
 bus_type : bus3


type (bus4) {
 base_type : array ;
 data_type : bit ;
 bit_width : 6 ;
 bit_from : 0 ;
 bit_to : 5 ;
 downto : true ;
}
bus (SCLK_DLY_SEL) {
 bus_type : bus4


type (bus5) {
 base_type : array ;
 data_type : bit ;
 bit_width : 4 ;
 bit_from : 0 ;
 bit_to : 3 ;
 downto : true ;
}
bus (SPARE) {
 bus_type : bus5

  cell (rx_clkgen_tdl) {
    area : 2025;
    cell_leakage_power : 0;
    dont_use : true;
    interface_timing : true;
    pg_pin (VDD) {
      direction : inout;
      pg_type : primary_power;
      voltage_name : "VDD";
    }
    pg_pin (VSS) {
      direction : inout;
      pg_type : primary_ground;
      voltage_name : "VSS";
    }
    pin ("BITS_CLK2QDLY[0]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.00132887;
      rise_capacitance : 0.00132887;
      fall_capacitance : 0.00132646;
    }
    pin ("BITS_CLK2QDLY[1]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.00132887;
      rise_capacitance : 0.00132887;
      fall_capacitance : 0.00132646;
    }
    pin ("BITS_DCC_MAIN[0]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000557936;
      rise_capacitance : 0.000557936;
      fall_capacitance : 0.000557719;
    }
    pin ("BITS_DCC_MAIN[1]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000557936;
      rise_capacitance : 0.000557936;
      fall_capacitance : 0.000557719;
    }
    pin ("BITS_DCC_MAIN[2]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000557936;
      rise_capacitance : 0.000557936;
      fall_capacitance : 0.000557719;
    }
    pin ("BITS_DCC_MAIN[3]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000557936;
      rise_capacitance : 0.000557936;
      fall_capacitance : 0.000557719;
    }
    pin ("BITS_DCC_MAIN[4]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000557936;
      rise_capacitance : 0.000557936;
      fall_capacitance : 0.000557719;
    }
    pin ("BITS_DCC_MAIN[5]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000557936;
      rise_capacitance : 0.000557936;
      fall_capacitance : 0.000557719;
    }
    pin ("BITS_DCC_MAIN[6]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.00193895;
      rise_capacitance : 0.00193895;
      fall_capacitance : 0.0019222;
    }
    pin ("BITS_FIXDLY_MAIN[0]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399907;
      rise_capacitance : 0.000399907;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_FIXDLY_MAIN[1]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399907;
      rise_capacitance : 0.000399907;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_FIXDLY_MAIN[2]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399907;
      rise_capacitance : 0.000399907;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_FIXDLY_MAIN[3]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399907;
      rise_capacitance : 0.000399907;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_FIXDLY_MAIN[4]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399913;
      rise_capacitance : 0.000399913;
      fall_capacitance : 0.00039965;
    }
    pin ("BITS_FIXDLY_MAIN[5]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399913;
      rise_capacitance : 0.000399913;
      fall_capacitance : 0.000399653;
    }
    pin ("BITS_FIXDLY_MAIN[6]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399913;
      rise_capacitance : 0.000399913;
      fall_capacitance : 0.000399653;
    }
    pin ("BITS_FIXDLY_MAIN[7]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399904;
      rise_capacitance : 0.000399904;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_NDE_DLY[0]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399904;
      rise_capacitance : 0.000399904;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_NDE_DLY[1]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399904;
      rise_capacitance : 0.000399904;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_NDE_DLY[2]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399904;
      rise_capacitance : 0.000399904;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_NDE_DLY[3]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399904;
      rise_capacitance : 0.000399904;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_NDE_DLY[4]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399904;
      rise_capacitance : 0.000399904;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_NDE_DLY[5]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399904;
      rise_capacitance : 0.000399904;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_NDE_DLY[6]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399904;
      rise_capacitance : 0.000399904;
      fall_capacitance : 0.000399639;
    }
    pin ("BITS_NDE_DLY[7]") {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000399904;
      rise_capacitance : 0.000399904;
      fall_capacitance : 0.000399639;
    }
    pin (BIT_HIRANGE) {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      capacitance : 0.000799716;
      rise_capacitance : 0.000799716;
      fall_capacitance : 0.000799202;
    }

can anyone let me know what to change in my script?

Asked By: san269605

||

Source

Answer 1

You need to read in the second file and parse it into the sections to add, storing those by name. Helpfully, you’ve separated them by a blank line; that makes it easy!

set file_temp [open "temp.txt" r]
set temp_contents [read $file_temp]
close $file_temp

# uffff is a Unicode character unlikely to occur in your input
set chunks [split [regsub -all {nn+} $temp_contents "uffff"] "uffff"]
set chunkIndex 0

Next, when you scan through the main file, when you find an insertion point you just use the next chunk.

set outputList {}
foreach line [split $temp_contents "n"] {
    if {[string first "bus(" $line] >= 0 && $chunkIndex < [llength $chunks]} {
        lappend outputList [lindex $chunks $chunkIndex]
        incr chunkIndex
    }
    lappend outputList $line
}
set output [join $outputList "n"]

This does positional splicing.

If you want to splice by name, you parse the chunks to splice to get the name to look them up by, store the chunks in an array, then in the splicer you look up what you’re going to insert and do that. I don’t currently understand what exact rules you would use for this, so I’ve not written it.

You may need to do additional work to fix up the resulting file. Sometimes, it is easier to do such things manually than to code up the rules for automating them. (If you’re automating, you are best working out how to decide whether the pieces in the main file represent complete parts. If you’re using { and } to denote sections of declaration, the Tcl info complete command might help.)

Answered By: Donal Fellows

Answer 2

open both files and check if the lines are more than zero, match the string as per your requirements, use for loop and read line by line (10 lines) and store this in variable, where the string will match add 10 lines from second file respectively.

set in_file [open "temp.txt" r]
set in_lib [open "rx_clkgen_tdl_ss_0.675v_m40c1.lib" r]
set out_file [open "rx_clkgen_tdl_ss_0.675v_m40c1_bus.lib" w]

# Read in_file line by line
while {[gets $in_lib line] >= 0} {

  # Check if line is "pin*[0]*"
  if {[string match {*pin*[0]*{} $line] == 1} {
    # Insert every 10 lines from temp.txt to the 2nd file before the line found
    for {set i 0} {$i < 10} {incr i} {
      set temp_line [gets $in_file]
      if {[eof $in_file]} {
        break
      }
      puts $out_file $temp_line
    }
    puts $out_file $line
  } else {
    # Write the line to the 2nd file
    puts $out_file $line
  }
}

# Close the input and output files
close $in_file
close $in_lib
close $out_file

feel free to edit explanation it will help for others also.

Answered By: san269605

In TCL Script/python script, add few lines of data where the specific line occurs

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